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**Instructors:**
John Dougherty

**Semester & Year:** Fall 2014

**Schedule:** Lecture: MW 2:30-4:00 in KINSC H108;
Lab on F 12:30-3:30, register for one hour slot

Recommended (or an acceptable alternate text): Computer Engineering: Hardware Design, by M. Morris Mano.

"The Haverford Educational RISC Architecture" by David Wonnacott (this booklet is available with a nice cover at the Haverford book store (the lulu.com version, but without the shipping cost) or you can print your own (without the cool cover) from the HERA web site).

**Requirements:**

- Exams covering each of the three sections of the course:(1) combinational circuits; (2) sequential circuits; and (3) system/microprocessor design.
- Lab exercises, including "live grading" sessions
- Written homework or "mini-homework"
- Class participation, including in-class assessments

**Collaboration:** You are encouraged to discuss the lecture material
and the labs and problems with other students, subject to the following
restriction: the only "product" of your discussion should be your
memory of it - you may not write up solutions together, or exchange written
work or computer files.

Collaboration is not allowed on exams.

**Prerequisites: **
CMSC 106 (or 206 at Bryn Mawr).
Math/CS 231 (Discrete Mathematics) is also highly recommended.
Concurrent enrollment in this and two other CMSC lab courses requires
permission of the instructor.

**Description:** A lecture/laboratory course studying the hierarchical
design of modern digital computers: combinatorial and sequential logic design,
memory and processor organization, instruction sets, assembly language,
elements of operating systems, and advanced topics as time permits (such as
parallel processing)

Lab Assignments:

- Lab 0: Introduction to logisim and Thinking About Circuits
- Lab 1: Boolean Logic and Combinational Circuits
- Lab 2: Modular Combinational Circuits
- Lab 3: Arithmetic
- Lab 4: Latches and Flip-Flops
- Lab 5: High-Level Sequential Circuits
- Lab 6: RTL and Memory Systems
- Lab 7: Microprocessors and Arithmetic (instruction memory, registers, partial ALSU, partial instruction decoding for the HERA microprocessor)
- Lab 8: Memory: Obtaining Instructions and Data (read/write data memory, decoding and execution of memory operations for the HERA microprocessor)

A preliminary syllabus is available,
but may be revised during the semester.

Page maintained by John Dougherty and
David Wonnacott. |